Many integrated circuits (ICs), including, for example, input/output (IO) buffers, etc., employ resistance compensation circuitry for compensating output termination resistances associated with the ICs. The resistance compensation circuitry generally attempts to minimize an overall variation of resistance as a function of process, supply voltage and/or temperature (PVT) conditions to which the ICs may be subjected. This in turn ensures proper matching of source termination resistances in the ICs to transmission line impedances of corresponding cables, backplanes, printed circuit board connections, etc., which may be coupled to the ICs.
A conventional resistance compensation circuit employs a parallel and/or series resistor switching scheme that is controlled by monitoring the resistance of a reference resistor for adjusting the resistance value of a compensated resistor comprising a plurality of resistor segments. The resistor segments forming the compensated resistor are typically selected to be of equal resistance value relative to one another. The overall resistance value of the compensated resistor is commonly adjusted by switching one or more resistor segments into or out of the circuit as required to match a desired impedance.
FIG. 1A is a schematic diagram depicting a compensated termination resistor circuit employing a parallel switching scheme to switch resistor segments R0, R1, R2 and R3, which are all of equal value relative to one another. Switches SW0, SW1, SW2 and SW3, used to selectively connect corresponding resistor segments R0, R1, R2 and R3, are controlled by control signals VSW0, VSW1, VSW2 and VSW3, respectively. The control signals VSW0, VSW1, VSW2, VSW3, are selected so as to provide equally spaced switching intervals for the resistor segments. However, having equally spaced resistance intervals does not typically minimize the overall resistance tolerance as a function of PVT conditions to which the circuit may be subjected. Moreover, this approach generally requires a higher number of intervals in order to realize a particular resistance tolerance, and is thus less efficient than certain inventive compensation methodologies, as will be described herein.
Accordingly, there exists a need for techniques for improving the efficiency of resistance compensation circuitry, which does not suffer from one or more of the problems exhibited by conventional resistance compensation methodologies.